a. Technical Field
The present invention relates to an apparatus for controlling on-die termination, and more particularly, to an apparatus for controlling on-die termination that is capable of improving calibration accuracy.
b. Related Art
In a high speed semiconductor apparatus, the swing widths of signals that interface with the semiconductor apparatus have decreased such that a delay time necessary for signal transmission has been minimized. However, when the swing width of a signal is reduced, the influence of external noise on the signal, and reflection of the signal is high due to the mismatching of impedances at an interface terminal. The mismatching of impedance occurs due to the external noise, variations in a power supply voltage, variations in the operation temperature, variations in the manufacturing processes, and the like.
When mismatching of impedance occurs, it is difficult for data to be transmitted at high speed, and data output from a data output terminal of a semiconductor device may be distorted. That is, when resistance is not appropriately matched, a transmitted signal is reflected, and it is likely for an error to occur during signal transmission.
Further, when an external fixed resistance is used in the semiconductor apparatus, the external impedance cannot be appropriately matched with the internal impedance because of aging of an integrated circuit, temperature variations in the integrated circuit, or differences in manufacturing processes. Thus, when a semiconductor apparatus receives a distorted signal through an input terminal, it may cause a problem such as a set-up/hold failure or an input level determination error.
In order to make an internal resistance (i.e., impedance) equal to an external reference resistance, a technique has been suggested in which the resistance of a termination-terminal is adjusted by adjusting the number of turned-on transistors among a plurality of transistors that are connected in parallel to one another.
Meanwhile, in a high speed semiconductor apparatus, an impedance matching circuit, called an on-chip termination or on-die termination is provided near a pad in an IC chip. In particular, various new concepts have been added in order to control the data transmitting speed in a DDR (Double Data Rate) memory apparatus. In all of them, resistance at the termination is necessary to achieve smooth signal transmission between elements.
FIG. 1 is a circuit diagram illustrating a structure of an apparatus for controlling on-die termination according to the related art.
The apparatus for controlling on-die termination (ODT) includes an on-die termination control unit 10, an external resistor R5, a comparator 20, a latch 30, and a counter 40.
In this case, the on-die termination control unit 10 includes a plurality of PMOS transistors P0 to P4, and a plurality of resistors R0 to R4 that are respectively connected to the plurality of PMOS transistors P0 to P4. The plurality of PMOS transistors P0 to P4 are supplied with a code signal <0:4> through respective gate terminals. The external resistor R5 is connected between the on-die termination control unit 10 and a ground voltage terminal, and is generally called a ZQ resistor in memory superior to DDR2.
The comparator 20 is supplied with the signal of a node A through a positive terminal + (namely the output signal of the on-die termination control unit 10), and is supplied with a reference voltage Vref having a value of VDD/2 through a negative terminal −.
The latch 30 latches the output of the comparator 20.
The counter 40 counts the output of the latch 30, and outputs a code signal code<0:4> using the counted latch signal.
The operation of the apparatus for controlling on-die termination according to the related art with the above-described structure will be described below.
First, the comparator 20 compares the output of the on-die termination control unit 10 and the reference voltage Vref, and outputs a high level signal or a low level signal.
For example, if the resistance of the on-die termination control unit 10 is smaller than the resistance of the external resistor R5, the voltage at the node A becomes larger than the reference voltage Vref, and node B, which is an output terminal of the latch 30, becomes a high level. Further, if the node B becomes a high level, a least significant bit (LSB) code in a five-bit code signal code<0:4> of the counter 40 increases by “1”. As such, if the code is increased by 1, a corresponding transistor among the plurality of PMOS transistors P0 to P4 of the on-die termination control unit 10 is turned off, and an on-die termination resistance increases.
Conversely, if the resistance of the on-die termination control unit 10 is larger than the resistance of the external resistor R5, the voltage at the node A becomes smaller than the reference voltage Vref, and the node B, which is the output terminal of the latch 30, becomes a low level. Further, if the node B becomes a low level, the least significant bit (LSB) code in the five-bit code signal code<0:4> of the counter 40 is decreased by ‘1’. As such, if the code decreases by 1, the corresponding transistor among the plurality of PMOS transistors P0 to P4 of the on-die termination control unit 10 is turned on, and the on-die termination resistance decreases.
As the on-die termination resistance decreases or increases, the resistance of the external resistor R5 becomes equal to the resistance of the on-die termination.
However, in the apparatus for controlling on-die termination according to the related art, an offset voltage Vos exists at a positive terminal + of the comparator 20. As a result, a voltage that corresponds to “the voltage of the node A+ the offset voltage Vos” is supplied to the comparator 20. Therefore, the comparator 20 compares the voltage at the node A plus the offset voltage Vos and the reference voltage Vref, and sets a different on-die termination resistance than the actual resistance of the external resistor R5.
In this case, it is not possible to implement accurate on-die termination according to the external resistance, and thus the accuracy of on-die termination calibration is not reliable. Further, the on-die termination and current characteristics of a driver cannot be improved. As a result, it is not possible to implement a high speed memory that requires a high frequency operation.